1. Field of Invention
The invention relates to a sampling front-end circuit, particularly to a high speed sampling front-end circuit without sample and hold circuit (non-sample/hold). Its direct application is in pipelined A/D converters.
2. Description of Related Arts
As to pipelined A/D converter design, chip power and size increase as sampling rate steps up. A sampling front-end circuit takes the largest size and consumes the most power of a pipelined A/D converter. Hence, a high speed sampling front-end circuit is in need featuring low power.
A sampling front-end structure is shown in FIG. 1 for conventional pipelined A/D converter with non-sample/hold, wherein a MDAC sampling network includes a switch Sm0, two capacitors C10, a comparator array including a switch Sf0 and two capacitors C20.
Time constant of a MDAC sampling network is expressed as equation (1)τMDC0=2C10·RSm0  (1)
Wherein, RSm0 is on-resistance of switch Sm0.
Time constant of a comparator sampling network is expressed as equation (2).
                              τ                      Comp            ⁢                                                  ⁢            0                          =                  2          ⁢                                    C              20                        ·                          1                              g                m                                                                        (        2        )            
Wherein, gm is transconductance of a front operational amplifier of comparators, (1/gm) is impedance of a front op-amp of comparators at sampling phase.
Network matching is required as equation (3)τMDC0=τComp0  (3)And,
                              g          m                =                              2            ⁢                          μ              n                        ⁢                                                            C                  ox                                ⁡                                  (                                      W                    L                                    )                                                            comp                ⁢                                                                  ⁢                0                                      ⁢                          I              D                                                          (        4        )                                          R                      S                          m              ⁢                                                          ⁢              0                                      =                  1                                    μ              n                        ⁢                                                            C                  ox                                ⁡                                  (                                      W                    L                                    )                                                            S                                  m                  ⁢                                                                          ⁢                  0                                                      ⁢                          V              DD                                                          (        5        )            
Wherein, μn is electron mobility, Cox is capacitance of gate oxidation per unit,
      (          W      L        )        comp    ⁢                  ⁢    0  is width/length ratio of an input transistors of comparator, ID is current through an input transistor of comparator,
      (          W      L        )        S          m      ⁢                          ⁢      0      is width/length ratio of an MDAC sampling switch, VDD is power voltage.
According to equations (1) to (5), equation (6) is expressed as follows:
                                          1                          g              m                                            R                          S                              m                ⁢                                                                  ⁢                0                                                    =                                                                                                  μ                    n                                    ⁢                                      C                    ox                                                                    2                  ⁢                                                            (                                              W                        L                                            )                                                              comp                      ⁢                                                                                          ⁢                      0                                                        ⁢                                      I                    D                                                                        ⁢                                          (                                  W                  L                                )                                            S                                  m                  ⁢                                                                          ⁢                  0                                                      ⁢                          V              DD                                =                                    C              10                                      C              20                                                          (        6        )            
According to expression (6), network matching requires resistance ratio equal to capacitance ratio. Resistance ratio is not only relevant to absolute value of transistor size, but to process constant, power voltage and currents through devices. It is obvious that network matching depends on multiple conditions which make it hard to precisely match resistance of switch Sm of a MDAC sampling network and impedance (1/gm) of front op-amp of a comparator array at sampling phase.
The mismatch of time constant leads to different input signals for a MDAC sampling network and a comparator sampling network at a time. The difference between two signals is taken as offset error of comparators.Ve_offset0=2πfin(τMDAC0−τComp0)  (7)
Wherein, fin is input signal frequency.
According to equation (7), on condition of a certain offset error of comparators, the larger the mismatch of time constant (τMDAC0−τComp0) is, the less input signal frequency fin the sampling network takes. In that way, the mismatch of the MDAC sampling network and the comparator array leads to a low tolerate input signal frequency for A/D converters.
A conventional sampling front-end structure for a non-sample/hold pipelined A/D converter is shown in FIG. 1. The feedback coefficient of the operational amplifier is expressed as equation (8):
                              β          0                =                                            C                              f                ⁢                                                                  ⁢                0                                                                    2                ⁢                                                                  ⁢                                  C                  10                                            +                              C                                  f                  ⁢                                                                          ⁢                  0                                                              =                      feedback_capacitance                                          2                ×                sampling_capacitance                            +              feedback_capacitance                                                          (        8        )            
Wherein, C10 is sampling capacitance, Cf0 is feedback capacitance. As the denominator has two times the sampling capacitance C10, the feedback coefficient is smaller. The smaller the feedback coefficient is, the larger power the circuit has. So two times of C10 is a major cause for large power consumption.
A time sequence diagram of a conventional sampling front-end structure for a non-sample/hold pipelined A/D converter is shown in FIG. 1. Sampling phase (Φ10) covers 50% of clock circle. Comparison phase (T_latch0) and amplification phase (Φ30) take the other 50%, which greatly shortens the time of amplification phase and decreases maximum sampling rate for A/D converters.